FAQ Foundry
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What does mean BEBO, BEMO, MENT, NTBO, NTMO and NTNT?
The delivered dies are classified according to a 4 digit code, coming from French acronymes: first 2 digits refer to the electric sorting (BE: good electrical, ME: bad electrical, NT: not sorted), last 2 digits refer to optical sorting (BO: good optical, MO: bad optical, NT: not sorted). E.g.: BEBO: good electrical/good optical chips, BEMO: good electrical bad optical chips and so on.
Which are the maximum currents per pad?
The maximum DC current per probe is 500 mA.
Are there any UMS recommendation for chip soldering?
Please refer to the Application Note AN0001 available on the UMS website.
How long can wafers be stored on film?
Tape is not set for storage but for shipment. Best practice is likely 6 months duration on tape.
How to remove UV tape?
Please contact Foundry support to get a specific documentation.
How to install ADS PDKs?
An installation guide is available in the Design Kit.
How to renew ADS PDK licence when expired?
The annual ADS keys can be directly downloaded from your account on the UMS website.
How work the UMS QFN services?
UMS provides access to qualified QFN plastic packaging platform for both GaN and GaAs technologies. A library of leadframe is available for customers to choose among UMS secured stock. A checklist allows to validate the circuit compliance with the package design rules. A minimum quantity is needed for the assembly. In case of development mask with few pieces per circuit, a dummy wafer can be bought to secure the setup of the assembly process.
Why do I need a DK agreement to get the PDK?
UMS PDK and DM contain confidential information on our technologies. The customer must commit to not transfer these information to other parties, neither to publish them in an article.
Why the DK agreement is only signed by the customer?
This document is an unidirectional agreement. In this phase, only UMS is sharing information on the technologies and these information should not be transferred to third parties or published. The results generated by the customers by using our technologies (circuit performances, comparisons, etc.) are instead customer IP, and can be published as they like. UMS is committed to protect their confidentiality.
Do I need an export licence in the frame of a Foundry run? How to apply and what is the timing?
An individual export licence is only required for countries other than the EU, Australia, Canada, Japan, New Zealand, Norway, Switzerland, the UK and the USA. In this case, customers have to fill in an End-of-Use Certificate (EUC) available on request. Validation of the licence by French regulations will take about 1 month.
Can we send the PDK to a different Unit of our Company?
A DK agreement is needed for each unit of the company and the access to the PDK/DM should be only provided by UMS. In particular, Units in different countries could be submitted to different export control constraints.
AMR
Absolute Maximum Ratings
AOI
Automatic Optical Inspection
BCB
Benzocyclobutene
BEBO
Good Electrical/Good Optical
BEMO
Good Electrical/ Bad Optical
DM
Design Manual
FLR
Final Launching Review
LAT
Lot Acceptance Test
MENT
Bad electrical/ not sorted optically
MPW
Multi Project Wafer
NTBO
Not sorted electrically/ good optical
NTMO
Not sorted electrically/ bad optical
NTNT
Not sorted electrically/ not sorted optically
OWT
On Wafer Test
PCM
Process Control Monitor
PDK
Process Design Kit
PDM
Process Development Monitor
ROR
Recommended Operating Ratings
SEM
Scanning Electron Microscopy
TCV
Technological Characterisation Vehicle
WAT
Wafer Acceptance Test
Can I modify the transistor or the diode layout?
The layout of the active devices cannot be modified. In case the customer wants to test a layout modification for development purposes, UMS can accept a derogation after checking the manufacturability of the proposed layout. Nevertheless, UMS cannot commit on neither the model accuracy, nor the device reliability (robustness and life-time) nor the manufacturability yield.
How can I draw a text on my circuit?
Use alphabet available in the ADS library (Miscellaneous palette) or gds file provided with Cadence AWR MWO PDK.
In which cases shall I use the pads of the PDK?
The use of the Pad cells provided into the PDK is mandatory in case of On-Wafer test or assembly in UMS, because these pads have the minimum sizes required for UMS services. Customers can use other pads dimensions and pitches if compatible with their measurements and/or assembly processes performed outside UMS.
Which are the layout constraints for OWT in UMS?
RF and DC pads from the PDK library are mandatory. It is recommended to have one grounded pad associated to each DC pad in order to ease external decoupling. The maximum number of pads per side is 15. The maximum DC current per probe is 500 mA.
Can I use the model in a region outside the validity domain?
The model can provide simulations outside the validity domain, based on extrapolation. Nevertheless, UMS will not commit on the model accuracy. Please, contact Foundry support for a dedicated analysis.
Which are the differences between a linear hot-FET model and a nonlinear hot-FET model?
A linear hot-FET model allows to choose the bias from a list of points and must be used for linear simulations only (S parameters and Noise Figure). A nonlinear hot-FET (NLHF) model must be used for all nonlinear simulations: in this case, DC sources have to be added into the schematic. The major part of the NLHF model does not include a noise model: for noise simulations the linear model must be used.
Difference between hot-FET and cold-FET
Cold-FET model: drain voltage is biased at 0V (switch function). Hot-FET model requires a drain voltage (for amplifier function).
How to use the option “via=yes/no” for degenerated transistors source vias?
With “via=yes”, the sources are directly grounded (2-port model). With “via=no” (3-port model), sources are accessible to connect other components (lines, inductors, etc.).
For more details, please refer to the Electricals Models chapter of the Design Manual.
Why does GH15 come with different technology versions?
GH15-1X family allows the customer to choose among several versions in order to get the most suitable process for the application: features for compact design, humidity protection or high-frequency optimized layout.
How to take into account BCB impact on circuit performances?
The BCB mechanical protection is taken into account in the PDKs in both electrical models and EM stack: please, refer to the Design Manual for instructions to enable this option.
Should I consider dicing street into the MMIC size for the MPW?
Indeed, you have to add 100 µm for GaN technologies or 70 µm for GaAs technologies to the dimension of the die frame.
What is included in a Shared Foundry run (MPW)?
The Shared Foundry run offer is limited to the manufacturing and shipment of 20 bare dies per circuit from a PCM good wafer, without measurement or optical inspection.
The list of authorised die sizes by technology is available on the UMS website.
Is it possible to go beyond the maximum ratings?
There are two kind of maximum ratings: ROR (Recommended Operating Ratings) and AMR (Absolute Maximum Ratings). The ROR should be respected to get long product life-time: it is possible to use the circuit beyond the ROR for a certain time (undefined and depending on the circuit conditions) but UMS will not guarantee neither the reliability nor the model accuracy. Using a circuit beyond the AMR can instead lead to catastrophic failures.
Which are the Space derating rules to be applied during the circuit design phase?
General space derating rules are the following: 75% of AMR if < ROR or ROR values.
Please check latest ESA standards at:
https://escies.org/webdocument/showArticle?id=167&groupid=6.
Which is the flow for wafer space qualification?
The Wafer Acceptance Test (WAT) is based on: DC and RF tests, space visual inspection Cond. A, wire bond & die shear tests, SEM.
Which is the useful surface on a 4-inches wafer?
About 6080 mm², value for GaAs and GaN.
Do I have to build the tile by myself?
UMS will take care of tile building in order to optimize the space and maximize the number of circuits. Customers can provide a tile drawing in case of specific request. Do not forget free area for PCM placement.
Which are the dimensions of the dicing streets?
The dicing street is a path free of any metallisation between each die to allow the singulation.
The dicing streets are 100 µm for GaN technologies and 70 µm for GaAs technologies, adding by UMS during the tile building.
How to use the die frame for circuit layout?
Circuit layout is delimited by the die frame. The final MMIC dimension (after dicing) = die frame + dicing streets.
How to place e-beam marks?
E-beam marks must be placed at the 4 corners of each circuit (same orientation for all circuits, horizontally or vertically).
Can I choose different orientation for transistor gates?
No, all the transistors and diodes gates must have the same orientation (horizontal).
Which is the tolerance after dicing?
A half dicing street should be considered for the tolerance (+/- 50 µm for GaN and +/- 35 µm for GaAs).
Which are the minimum chip dimensions?
The recommended minimum chip size is 800 um x 800 um, mainly for dicing constraints and also dimensions of the PCM cells to be inserted in the tile.