Technologies – Back-End (Packaging)
UMS is performing in-house and also in collaboration with external partners the back-end process that transforms a completed front-end wafer to finished electrical components. Backend semiconductor processes are highly complex, and it requires contributions from highly trained specialists from a number of different disciplines: materials science, chemistry, physics, and mechanical and electrical engineering. Data science drives conformance testing and yield optimization. It is the final step in chip manufacturing, and is a collaborative, multidisciplinary effort.
Completed front-end wafers are the input to the process. Generally, there is no restriction on the diameter (4”-12”) nor the type of semiconductor technology (III-V, Si), but there are specific tooling requirements. The wafers are subjected to a series of steps including wafer thinning to a desired thickness then followed by die singulation. There are typically several test insertions within the process to identify non-conforming material. Finally, known good die are packaged in a form that is adapted to the targeted application. A final assessment is performed to ensure conformance. The basic sequence is shown below.
Figure: an micrograph of a finished UMS wafer taken just prior to die singulation.
Figure: an micrograph of a finished UMS wafer taken just prior to die singulation.
Figure: a cartoon representing the transformation of a semiconductor die into a package. Example shown is a QFN type.
Packaging refers to all the encapsulation and interconnection technologies to ensure the protection and proper functioning of chips during their life cycle.
The 5 Objectives of Packaging
1. Establish the electrical connectivity between the die to the external world, often a printed circuit board (PCB)
This requires an adaptation between the vastly different scales – the dimensions of the wiring on the die to the wiring available at its interface. To illustrate, the wiring dimensions on the die are typically in the micrometer (10-6 m) scale while the dimensions on a PCB are typically many orders of magnitude higher and in the millimeter (10-3 m) scale. For many performance critical applications including RF/mmW, the means in which this is done to ensure that the performance of the die is minimally impacted.
2. Protect the die from the environment in which it will operate
The semiconductor die are insufficiently robust to sustain the various forces exerted onto it when placed into the intended application. Stress from mechanical bending or stresses generated from thermal gradients can result in catastrophic damage. Moreover, the semiconductor die are insufficiently robust to resist humidity and chemical exposure. An appropriate encapsulation method is selected that best meet the application and client requirements for performance and cost.
3. Protect the die from overheating
The semiconductor die generates often significant heat, and this heat must be effectively dissipated else it will result in accelerated failure. As an example, a RF power amplifier is unfortunately imperfect in converting DC energy to RF, and this wasted energy is converted to heat. Various methods and techniques are available to address such challenges, and this is probably the most important consideration that must be addressed early within the product design phase.Add your answer here…
4. Expand the functionality, enhance performance, or reduce cost
Add yourIt is possible to combine different semiconductor die together into a single package, where each is a different front-end wafer technology, manufactured independently. This approach creates opportunities to reduce cost, by partitioning some functions in a lower cost technology rather than pursing a monolithic approach with higher cost technology. Alternatively, the combination of different technologies can expand the functionality. A monolithic approach many not be at all technically feasible. As an example, III-V technologies have state of the art RF performance but lack digital control, memory, and logic functionality that are strengths of a Si technology. The integration of the two semiconductor die into a single package would expand the functionality beyond either the individual Si or III-V die. Finally, partitioning the functionality to combine different die, each from a different wafer technology, and each having been selected for the optimum performance at that particular task would enhance the performance over a monolithic approach. As an example, one could combine a GaAs pHEMT die for the receive path with a GaN HEMT die for the transmit path of a radio link. answer here…
5. Standardization
The location of the electrical connections and mechanical constraints for a given package type are standardized. Broad industry standards facilitate ease of use for clients to use UMS components to create more complex sub-assemblies quickly and cheaply. Moreover, repair or replacement is straightforward. There are a multitude of different packages available to serve a very diverse set of applications. More details are available at this link.
UMS offers a range of different, standardized package types to address our core markets.
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